Field
Various features relate to facilitating accelerated communication and transfer of data between chips or processors.
Background
Many electronic devices include multiple processors that perform distinct functions during operation. However, during startup or boot-up of the electronic device, these processors must load instructions (e.g., boot images or software images) to operate. In certain implementations, support or auxiliary chips (e.g., processors) obtain such instructions or software from another chip, like an application processor, through a chip-to-chip interface.
Some devices (e.g., PCIe capable devices) with an application processor (“AP”) that require an executable software image can store their software images onboard in either a boot ROM chip or in persistent file storage mechanism (e.g., NAND/NOR flash). Both these alternatives are cost and time inefficient.
Another alternate scheme includes a device driver on the application processor that memory maps the device RAM and copies the software images directly into device RAM. This approach requires involvement of the application processor and results in sub-optimal application processor throughput. Thus, current chip-to-chip data transfer approaches are costly, time intensive, and/or suboptimal.